Solve the following, in English

The inputs are two 2-bit binary numbers, AB and CD, meaning A, B, C, D are individual bits. The outputs L, G, E are high (1) based on the comparison of AB and CD: L is high when AB < CD, G is high when AB > CD, and E is high when AB = CD.

Using comparator logic, the simplified Boolean expressions for L, G, and E are:

The circuit diagram is constructed using standard logic gates based on the Boolean expressions.
Let $X_{AC} = A \text{ XNOR } C$ and $X_{BD} = B \text{ XNOR } D$.

• For E: An AND gate takes $X_{AC}$ and $X_{BD}$ as inputs.
• For L:
  • An AND gate takes $A'$ (NOT A) and $C$ as inputs.
  • Another AND gate takes $X_{AC}$, $B'$ (NOT B), and $D$ as inputs.
  • An OR gate takes the outputs of these two AND gates as inputs.
• For G:
  • An AND gate takes $A$ and $C'$ (NOT C) as inputs.
  • Another AND gate takes $X_{AC}$, $B$, and $D'$ (NOT D) as inputs.
  • An OR gate takes the outputs of these two AND gates as inputs. This circuit requires two XNOR gates, four NOT gates, five AND gates, and two OR gates.

• $-35 + (-11)$

  • Convert $35_{10}$ to 8-bit binary: $00100011_2$.
  • 2's complement of $35_{10}$ (for $-35_{10}$): $11011101_2$.
  • Convert $11_{10}$ to 8-bit binary: $00001011_2$.
  • 2's complement of $11_{10}$ (for $-11_{10}$): $11110101_2$.
  • Add the 2's complement numbers: $$\begin{array}{r} 11011101_2 \quad (-35_{10}) \\ + \quad 11110101_2 \quad (-11_{10}) \\ \hline 111010010_2 \quad (-46_{10}) \end{array}$$ Discard the carry-out. The 8-bit result is $\boxed{\text{}11010010_2}$.

• $19 - (-4)$

  • This is equivalent to $19 + 4$.
  • Convert $19_{10}$ to 8-bit binary: $00010011_2$.
  • Convert $4_{10}$ to 8-bit binary: $00000100_2$.
  • Add the binary numbers: $$\begin{array}{r} 00010011_2 \quad (19_{10}) \\ + \quad 00000100_2 \quad (4_{10}) \\ \hline 00010111_2 \quad (23_{10}) \end{array}$$ The 8-bit result is $\boxed{\text{}00010111_2}$.

Add $(93)_{16}$ and $(DE)_{16}$:

• Rightmost column: $3 + E = 3 + 14 = 17_{10}$. This is $1_{16}$ with a carry of 1.
• Leftmost column: $9 + D + 1 (\text{carry}) = 9 + 13 + 1 = 23_{10}$. This is $7_{16}$ with a carry of 1.
• Final carry: 1. The sum is $\boxed{\text{}171_{16}}$.

• NOT gate using NAND gates: A NOT gate can be created by connecting both inputs of a NAND gate to the same input signal. If the input is $A$, the output is $(A \cdot A)' = A'$.

  $$\text{A} \longrightarrow \text{NAND} \longrightarrow \text{A'}$$

• OR gate using NAND gates: An OR gate can be created using three NAND gates, based on De Morgan's theorem: $A + B = (A' \cdot B')'$.

  1. Invert input $A$ using a NAND gate to get $A'$.
  2. Invert input $B$ using a NAND gate to get $B'$.
  3. Feed $A'$ and $B'$ into a third NAND gate. The output will be $(A' \cdot B')' = A'' + B'' = A + B$.
  $$\begin{array}{rcl} \text{A} & \longrightarrow & \text{NAND} \longrightarrow \text{A'} \\ \text{B} & \longrightarrow & \text{NAND} \longrightarrow \text{B'} \\ \text{A'} & \longrightarrow & \text{NAND} \longrightarrow \text{A+B} \\ \text{B'} & \longrightarrow & \end{array}$$